Gate Drive Technology
ICERGi have developed state-of-the-art magnetic-coupling technologies TruDrive™ allowing precise and fully-isolated driving of a family of semiconductor devices including GaN, Si, and SiC. TrueDrive™ features innovative transmission of drive signal and power on the same channel, resulting in significant reduction in both magnetics sizes and manufacturing complexity, and at the same time obviating the need for boot-strap diodes or local floating power sources. The technology finds its applications in both single and dual floating gate drivers. The later products are designed to drive a “half-bridge” series connection of devices in a complementary manner with inherent interlock protection against shoot-through conditions. All ICERGi drivers feature low-intrinsic cost, compact form factor with “drop-in” design capability, accurate operation with fast propagation times, and galvanic isolation (optionally to 5kV rating). Benchmarking our drivers against the existing market is visually captured in Fig. 1 below. TruDrive™ addresses many of the latent issues of current driver technologies and has been described as being the “near ideal” driver.
Fig. 1 Gate Driver Technology Benchmarking – 600V+ Types (larger area is better)
At it’s core, the ICERGi gate driver uses two small transformers to convert pulse inputs (rising/falling edge) into an isolated PWM signal for driving power devices. This design offers inherent interlocking functionality and in the absence of any input pulses, the output defaults to a safe low state. Comparison of conventional vs. ICERGi approaches to gate driver design is illustrated in Fig. 2 below.
Fig. 2 Gate Driver Technology
ICERGi Gate Drivers are applicable to driving low-side and high-side, or any floating power devices like in multilevel converters, and are ideally suited for driving complementary devices. The IC92-xxx range deployment scenarios include traditional PWM and ICERGi pulse-drive approaches as illustrated in Fig. 3 below.
Fig. 3 Gate Driver Deployment Scenarios
Transistor Stacking & Voltage Sharing
Table I. Comparison between 300V and 150V MOSFETs
Fig. 4 Three implementations of Full-Bridge Totem-Pole Converter. Conventional Totem-pole Converter (left), 3-Level Totem-Pole Converter (center), 3-Level Totem-Pole Converter with stacked transistors (right)
a) ON/OFF pulse inputs and gate voltage waveforms
b) Zoom-in on ON pulse
c) Zoom-in on OFF pulse
Fig. 5 shows experimental drive waveforms of two MOSFETs in series along with ON and OFF pulses output by a microcontroller. Pulse width is the same for both types and set to 120ns. By studying turn-on and turn-off transitions in detail, one can confirm that two drive channels are almost identical and have minimal time offset, i.e. much less than 1ns. Slight offset in pull-down voltage levels occurs during off state but this should have no effect on either voltage sharing or device life span. Drive voltage during ON and OFF transitions seems to be very clean and healthy, i.e. monotonic increase/decrease with no visible sign of a Miller plateau region. Another interesting observation in Fig. 5 is that the propagation delay from the microcontroller to MOSFETs is quite short. The worst case is at turn-off and this is still less than 10ns. This feature is highly beneficial to applications running at MHz frequencies.