APEC 2019

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ICERGi team will be presenting a paper titled “99% Efficiency 3-Level Bridgeless Totem-pole PFC Implementation with Low-voltage Silicon at Low Cost”.

Achieving 99% efficiency for totem-pole PFC front-end stages with wide band gap (WBG) devices is no longer seen as a rare accomplishment. Design concerns revolving around the maturity of WBG technologies, the lack of dual sources, and very high component costs, lead to a quest for a medium-term low-cost mature silicon-based solution. Given poor reverse recovery performance associated with high-voltage (above 600V) Super-junction MOSFETs, existing approaches generally deploy boundary conduction mode (BCM) and interleaving for switching loss and EMI benefits. This makes control and system design relatively complex, costly, and as a result unattractive to cost-sensitive applications. Therefore, this article proposes a simple yet highly-efficient PFC implementation based on a 3-level bridgeless totem pole topology and 150V MOSFETs. The proposed solution is demonstrated in a complete 3kW PFC stage prototype in a compact form factor of 50mm x 260mm x 1U with an ultra-high efficiency exceeding 99% at 230V.